With the increased popularity of clocked portable digital circuits, it has become increasingly important to enhance the operational life of such systems. For example, it is known that so-called lap top and palm top computers can operate with a rechargeable battery or two AA battery cells for between 4 and 8 hours of running time. Once the power source becomes discharged it becomes necessary for the user to recharge the cells or replace the batteries.
Conventional digital systems include a circuit for generating a clock signal such as shown in FIG. 1. A crystal oscillator 20 is provided for generating an oscillating signal. A first resistor 22 is coupled in parallel across the crystal oscillator 20. A first capacitor 24 is coupled between a first terminal of the crystal oscillator 20 and ground. A second capacitor 26 is coupled between the second terminal of the crystal oscillator 20 and ground.
A second resistor 28 is coupled between the second terminal of the crystal oscillator 20 and a clock output terminal 32. A buffer 30 is coupled between the first terminal of the crystal oscillator 20 and the clock output terminal 32. Typically the buffer is an inverting amplifier. A clock signal is applied to the digital system via the clock output terminal 32. It will be apparent to those of ordinary skill in the art that the crystal oscillator 20, the resistors 22 and 28 and the capacitors 24 and 26 are typically formed of so-called external components while in many modern systems the buffer 30 is formed of a portion of an integrated circuit.
Unfortunately, the power drawn by the circuit of FIG. 1 increases as the clock frequency increases. Indeed, in some systems, the clock generating circuit can be the main source of power usage. For portable systems, the faster the clock operates, the higher the current drawn by the system. In effect this lowers the life of the batteries or storage cells. To overcome this problem, others have tried two principle approaches in the prior art.
A first prior art approach to limiting the power drawn by the clock generating circuit is to remove power from the oscillating circuit when the digital system is not in use. In particular, the power is removed from crystal 20. Though this approach significantly reduces the average power drain of the clock generating circuit, this approach does negatively impact the overall performance of digital system. For example, it generally takes between 1 millisecond and 1 second for a system to return to a stable operating frequency after initiating a restart operation from such a powered down condition. Accordingly, this approach is not generally desirable as it significantly reduces system performance.
A second approach to limiting the power drawn by the clock generating circuit is to establish a slow running clock generating circuit by operating the crystal oscillator 20 at a slow frequency. Because the crystal is operating more slowly, this technique draws much less power in the clock generating circuit. However, a frequency multiplying circuit is then required to increase the frequency to the desired level. Power drain improvement can be provided by eliminating power drawn by the multiplier circuit during inactive periods. Though not as deleterious as the first approach, it typically takes between 10 and 20 milliseconds for circuits using this second approach to lock onto a stable operating frequency.
FIG. 2 shows a block diagram of a clock generating circuit. The invention is embodied in the charge pump circuit 144. An oscillator circuit 140 such as that shown in FIG. 1 generates a first clock signal that is coupled to a divider 141 which in turn is coupled to a phase detector circuit 142 such as commonly found in the prior art. The divider 141 and phase detector circuit 142 is also commonly known as a frequency synthesizer circuit. The phase detector 142 generates two signals which are coupled as an up signal and a down input signal to the charge pump circuit 144 of the present invention. The charge pump circuit generates a voltage signal at a predetermined voltage level which is coupled to a voltage controlled oscillator circuit 146. The oscillator 146 can be any well known oscillator such as a ring oscillator. The output of the oscillator circuit 146 is coupled to a divider 147 which in turn is coupled as a second input to the phase detector circuit 142. The phase detector circuit 142 will develop its output signals to cause the charge pump to vary the voltage if the frequency of the oscillator circuit is different from a predetermined ratio of the output of the crystal oscillator circuit 140. The output of the oscillator circuit 146 is also coupled to any well known buffer circuit 148 and is applied to a digital circuit (not shown).
FIG. 3 shows a charge pump input to a prior art clock frequency multiplier circuit. This circuit develops an output voltage that is used to control a voltage controlled oscillator (VCO). The VCO generates the clock signal used by the digital system; the lower the output voltage of this circuit, the faster the clock signal generated in the VCO. The circuit includes two inputs 40 and 42. A charge is maintained on the capacitor network including capacitors 56 and 60. An up input 40 triggers the circuit to generate a falling edge to raise the voltage charge on the capacitor network and a down input 42 triggers the circuit to generate a rising edge to reduce the voltage charge on the capacitor network.
The up input 40 is coupled to the input of an inverting output buffer 44 having an output which in turn is coupled to the input of an inverting output buffer 46. The output of the buffer 46 is coupled to the gate of a P-channel MOS transistor 48. The source of the transistor 48 is coupled to a supply voltage VDD and the drain is coupled to the drain of an N-channel MOS transistor 52 and the first terminal of a resistor 54. The down input 42 is coupled to the input of an inverting output buffer 50 having an output coupled to the gate of the transistor 52. The source of the transistor 52 is coupled to ground.
The second terminal of the resistor 54 is coupled to an output node 62 which controls a voltage controlled oscillator VCO, which is not shown here. A common example of such a VCO circuit is a ring oscillator. A capacitor 56 is coupled between the output node 62 and ground. The first terminal of a resistor 58 is coupled to the output node 62. A capacitor 60 is coupled between the second terminal of the resistor 58 and ground.
Once the power is removed from this circuit, the voltages stored on the two capacitors 56 and 60 decays due to parasitic losses. If the transistor 52 is left in the on state, it will discharge the node 62 even more quickly. In addition, there exists a potential path for power dissipation through the two transistors 48 and 52. Thus, upon power up, the voltage applied to the VCO is at a significantly lower level so that the clock signal generated by the VCO is too fast. The clock signal generated by the VCO will not return to its predetermined designed frequency until the output voltage of the charge pump returns to its predetermined level.
For a variety of reasons, some digital systems cannot operate properly with a clock signal at too fast a frequency. It is possible that the frequency is so fast that the synthesizer will fail to operate. Even if the oscillator operates, the divider may fail to function properly thereby causing the phase detector to fail because there is no appropriate input signal. Those systems will need to have the clock signal withheld until the signal approaches the desired frequency further reducing the system performance.
What is needed is a clock generating circuit that draws less power. What is also needed is a clock generating circuit that can stabilize to the desired frequency within a predetermined short time.